Differential signal comparator

ABSTRACT

There is provided a differential signal comparator which maintains the duty ratio of complementary input signals. The differential signal comparator includes differential amplifier circuits  1  and  2  receiving complementary input signals, a plurality of current amplifier circuits  3  to  6  for amplifying current output from the differential amplifier circuits and a current arithmetic operation circuit  7  for an arithmetic operation of an output from the plurality of current amplifier circuits  3  to  6  at the time of converting the differential signal between the complementary input signals into a voltage of CMOS level, wherein a capacitive load of an output of the differential amplifier circuit is constant independent of a level of the input signals. A voltage signal which is current-voltage converted to a complementary CMOS level signal is input into a differential comparator to obtain a single end CMOS level signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a differential signal comparator whichhandles a differential signal.

2. Description of the Related Art

A high-speed differential interface circuit is used according as signalshave been increased in speed in recent years, typified by a reducedswing differential signaling (RSDS) or a low voltage differentialsignaling (LVDS).

In these circuits, a differential signal is used as an input signal, sothat a voltage comparator circuit with a differential input is used inthe receiver circuits. The input differential voltage requires adifferential signal component of ±50 mV and common mode signal componentof so-called rail-to-rail (power supply to GND).

The differential signal comparator which handles such a differentialsignal is an application of a differential amplifier. A circuit, as anexample of a differential amplifier circuit, is disclosed in JapanesePatent Application Laid-Open No. 2006-148364. FIG. 5 illustrates thedifferential amplifier circuit in the application. The figure includesinput differential pairs DF61 and DF62, current mirrors CM61 to CM64 andconstant currents I61 and I62.

In the circuit structure illustrated in FIG. 5, when the input signal isin the vicinity of rail-to-rail, for example, in the vicinity of GND,only the input differential pair DF61 operates. For this reason, if theinput voltage is:

-   (1) In⁺>In⁻ and-   (2) In⁺<In⁻,    with the same constant current I61, in the above case (1), the    current mirror CM61 with the ratio of 1:1 is driven, and in the    above case (2), the current mirror CM62 with the ratio of 1:k is    driven. For this reason, there exists difference in a load between    the cases (1) and (2), that is to say, difference in the node    parasitic capacitances across the gate portions of the current    mirrors CM61 and CM62. The difference in the load makes the response    of the current mirror asymmetric, creating a problem in that the    current mirror generates a voltage comparison output whose duty    ratio is different from the duty ratio of the input signal.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a differential signalcomparator which maintains the duty ratio of a complementary inputsignal.

A differential signal comparator according to the present invention ischaracterized by including a differential amplifier circuit receivingcomplementary input signals and a plurality of current amplifiercircuits for amplifying current output from the differential amplifiercircuit, so as to convert the differential signal between thecomplementary input signals into a voltage of CMOS level, wherein thedifferential signal comparator further includes a current arithmeticoperation circuit for an arithmetic operation of an output from theplurality of current amplifier circuits, and a capacitive load of anoutput of the differential amplifier circuit is constant independent ofa level of the input signals. In the present invention, a voltage signalwhich is current-voltage converted to a complementary CMOS level signalis input into a differential comparator to provide a single end CMOSlevel signal.

According to the present invention, it is enable to obtain a CMOS leveloutput which suppresses the impairment of a duty ratio for arail-to-rail common mode input signal and a small-amplitude differentialinput.

Further features of the present invention will become apparent from thefollowing description of exemplary embodiments with reference to theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of the differential signal comparator ofthe present invention.

FIG. 2 is a circuit diagram illustrating one embodiment of thedifferential signal comparator of the present invention.

FIGS. 3A and 3B are graphs illustrating simulation results on thepresent invention.

FIG. 4 is a circuit diagram illustrating further in detail the circuitin FIG. 2.

FIG. 5 is a circuit diagram illustrating a conventional differentialsignal comparator.

DESCRIPTION OF THE EMBODIMENTS

An exemplary embodiment for carrying out the invention is described indetail with reference to the drawings. FIG. 1 illustrates a schematicdiagram of the differential signal comparator according to the presentinvention. In the figure, the differential signal comparator includes afirst differential amplifier circuit 1 and a second differentialamplifier circuit 2. Differential signals are input into input terminalsIn⁻ and In⁺ of the first and the second complementary differentialamplifier circuit 1 and 2. A common mode voltage input into inputterminals In⁻ and In⁺ is set within the range of from 0 V to the powersupply voltage and the differential voltage to be applied is within therange of from 0.1 V to 3 V.

The output current of the first differential amplifier circuit 1 isinput into two current amplifier circuits 3 and 4 which have the sameload capacitance. The output current of the second differentialamplifier circuit 2 is input into two current amplifier circuits 5 and 6which have the same load capacitance.

The output current of the current amplifier circuits 3 to 6 is processedin a current arithmetic operation circuit 7 to deliver a complimentarycurrent output. In addition, the current output is converted to avoltage output by a current-voltage conversion circuit 8 and then inputinto a differential comparator 9 to be converted to a single end CMOSlevel signal. Incidentally, the term “CMOS level” represents a voltagelevel within the range of from GND to the power supply voltage.

FIG. 2 is a circuit diagram illustrating a concrete example of thedifferential signal comparator in FIG. 1. The differential signalcomparator according to the present embodiment includes a firstdifferential pair DF21 with PMOS transistors MP21 and MP22 and a seconddifferential pair DF22 with NMOS transistors MN21 and MN22. The firstdifferential pair DF21 corresponds to the first differential amplifiercircuit 1 in FIG. 1 and the second differential pair DF22 corresponds tothe second differential amplifier circuit 2.

The differential signal comparator further includes first, second, thirdand fourth current mirror circuits CM21, CM22, CM23 and CM24. The firstcurrent mirror circuit CM21 corresponds to the current amplifier circuit3 in FIG. 1 and the current mirror circuit CM22 corresponds to thecurrent amplifier circuit 4. The current mirror circuit CM23 correspondsto the current amplifier circuit 5 and the current mirror circuit CM24corresponds to the current amplifier circuit 6.

The differential signal comparator still further includes fifth, sixth,seventh and eighth current mirror circuits CM25, CM26, CM27 and CM28.The fifth and the sixth current mirror circuit CM25 and CM26 correspondto the current arithmetic operation circuit 7 in FIG. 1. The seventh andthe eighth current mirror circuit CM27 and CM28 correspond to thecurrent-voltage conversion circuit 8 in FIG. 1.

The differential signal comparator is provided with constant currentsources 121 and 122 and a differential comparator CP. The differentialcomparator CP corresponds to the differential comparator 9 in FIG. 1.The current mirror circuits CM21, CM22, CM25 and CM26 each have twooutput terminals.

The input terminal of the first current mirror circuit CM21 is connectedto the drain of the PMOS transistor MP21 of the first differential pairDF21 and the common source electrode thereof is connected to GND. Afirst output terminal out of the two output terminals of the firstcurrent mirror circuit CM21 is connected to the input terminal of thecurrent mirror circuit CM27 along with the first output terminal of thecurrent mirror circuit CM25. The other second output terminal isconnected to the second output terminal of the current mirror circuitCM25 and the output terminal of the current mirror circuit CM28 andforms a first output (Ic⁺) which is a non-inversion input of thecomparator CP.

The input terminal of the second current mirror circuit CM22 isconnected to the drain of the PMOS transistor MP22 of the firstdifferential pair DF21 and the common source electrode thereof isconnected to GND. A first output terminal out of the two outputterminals of the second current mirror circuit CM22 is connected to theinput terminal of the current mirror circuit CM28 along with the secondoutput terminal of the current mirror circuit CM26. The other secondoutput terminal is connected to the first output terminal of the currentmirror circuit CM26 and the output terminal of the current mirrorcircuit CM27 and forms a second output (Ic⁻) which is an inversion inputof the comparator CP.

The input terminal of the third current mirror circuit CM23 is connectedto the drain of the NMOS transistor MN21 of the second differential pairDF22 and the common source electrode thereof is connected to the powersupply. The output terminal of the third current mirror circuit CM23 isconnected to the input terminal of the current mirror circuit CM25.

The input terminal of the fourth current mirror circuit CM24 isconnected to the drain of the NMOS transistor MN22 of the seconddifferential pair DF22 and the common source electrode thereof isconnected to the power supply. The output terminal of the fourth currentmirror circuit CM24 is connected to the input terminal of the currentmirror circuit CM26.

The current mirror ratio of the first current mirror circuit CM21 to thesecond current mirror circuit CM22 is 1:k, and the current mirror ratioof the third current mirror circuit CM23 to the fourth current mirrorcircuit CM24 is 1:m. The current mirror ratio of the fifth currentmirror circuit CM25 to the sixth current mirror circuit CM26 is 1:n andthe current mirror ratio of the seventh current mirror circuit CM27 tothe eighth current mirror circuit CM28 is 1:1. The relationship among k,m and n is represented by k=m×n.

The constant current source 121 is connected between the sources of thePMOS transistors MP21 and MP22 of the first differential pair DF21 whichare commonly connected together and the power supply. The constantcurrent source 122 is connected between the sources of the NMOStransistors MN21 and MN22 of the second differential pair DF22 which arecommonly connected together and GND.

In the differential signal comparator, the gate of the PMOS transistorMP21 is connected to the gate of the NMOS transistor MN22, which istaken to be a non-inversion input terminal In⁺. In addition, the gate ofthe PMOS transistor MP22 is connected to the gate of the NMOS transistorMN21, which is taken to be an inversion input terminal In⁻. Thus, theinput differential pair is formed by combining the N-channel MOSdifferential pair with the P-channel MOS differential pair, enablingsubstantial GND level to power supply voltage to be input.

The present invention is an application of a differential amplifierhaving rail-to-rail input capability. In general, a differentialamplifier having rail-to-rail input capability includes three modesaccording to input signals. The first mode is a domain where the commonmode electric potential of an input signal is too low to obtain a drainelectric potential which the constant current source 122 requires forits operation and only the first differential pair DF21 operates.

The second mode is a domain where both constant current sources 121 and122 can operate and both first and second differential pairs DF21 andDF22 operate. The third mode is a domain where the common mode electricpotential of an input signal is too high to obtain a drain electricpotential which the constant current source 122 requires for itsoperation and only the second differential pair DF22 operates.

The operation of the present embodiment is described below. The draincurrent of the PMOS transistor MP21 is taken to be Ip21 and the draincurrent of the PMOS transistor MP22 is taken to be Ip22, and if thedrain current of the NMOS transistor MN21 is taken to be In21 and thedrain current of the NMOS transistor MN22 is taken to be In22, the inputand the output current of each current mirror circuit are given below.The current mirror circuits CM21, CM22, CM25 and CM 26 each have twooutput terminals and the output current given below represents eachcurrent of the two output terminals.

The input current of CM21; Iin21=Ip21

-   The output current of CM21; Iout21=k×Iin21=K×Ip21-   The input current of CM22; Iin22=Ip22-   The output current of CM22; Iout22=k×Iin22=K×Ip22-   The input current of CM23; Iin23=In21-   The output current of CM23; Iout23=m×Iin23=m×In21-   The input current of CM24; Iin24=In22-   The output current of CM24; Iout24=m×Iin22=m×In22-   The input current of CM25; Iin25=Iout23=m×In21-   The output current of CM25; Iout25=m×n×Iin22=k×In21-   The input current of CM26; Iin26=Iout24=m×In22-   The output current of CM26; Iout26=m×n×Iin22=k×In22-   The input current of CM27; Iin27=k×Ip21+m×n×In21=k×(Ip21+In21)-   The output current of CM27; Iout27=k×(Ip21+In21)-   The input current of CM28; Iin28=k×Ip22+m×n×In22=k×(Ip22+In22)-   The output current of CM28; Iout28=k×(Ip22+In22), therefore, the    non-inversion input current Ic⁺ of the differential comparator can    be given by the following equation:    Ic ⁺ =k×(Ip21+In21)−(Iout22+Iout26)=k×{(Ip21+In21)−(Ip22+In22)}.

The inversion input current Ic⁻ of the differential comparator can begiven by the following equation:Ic ⁻ =k×(Ip22+In22)−(Iout22+Iout25)=k×{(Ip22+In22)−(Ip21+In21)}.

The above equation is used to calculate current in the second mode, butit is also effective for the other two modes. That is to say, settingsmay be performed as follows:

-   in the first mode, In21=In22=0, and-   in the third mode, Ip21=Ip22=0.

The currents Ic⁺ and Ic⁻ charge and discharge parasitic capacityexisting in the input node of the comparator, however the current mirrorcircuit outputs a high-impedance constant current and its electricpotential will be a level in the vicinity of from the power supply toGND according to the direction of the output current. In addition, ascan be seen from the above current equations of Ic⁻ and Ic⁺, they arecomplementary output of current and converted into a complementaryvoltage signal substantially equal to CMOS level.

The complementary voltage signal is input into the differentialcomparator to deliver a CMOS single end output faithful to the dutyratio of the input signal.

FIGS. 3A and 3B are graphs illustrating the input and output waveform.FIG. 3A illustrates complementary signals input into the differentialcomparator. FIG. 3B illustrates the waveform output from thedifferential comparator. Combining the voltage waveform 31 with thecomplementary voltage waveform 32 in FIG. 3A to provide an output whichis a highly accurate duty ratio with respect to the input signal asshown in FIG. 3B. The voltage waveform 31 in FIG. 3A is a non-inversionwaveform input into the differential comparator CP. The voltage waveform32 is an inversion input waveform.

FIG. 4 is a further detailed diagram of the circuit illustrated in FIG.2 and concretely illustrates each current mirror circuit. FIG. 4 showsthe current mirror ratio of each current mirror circuit described above.In this example, the current mirror ratio of the first and the secondcurrent mirror circuit CM21 and CM22 is taken to be 1:4, that of thethird and the fourth current mirror circuit CM23 and CM24 is taken to be1:2. In addition, the current mirror ratio of the fifth and the sixthcurrent mirror circuit CM25 and CM26 is taken to be 2:1 and that of theseventh and the eighth current mirror circuit CM27 and CM28 is taken tobe 1:1.

Although the differential signal comparator in the above embodiment isconfigured by using MOS transistors, the comparator may be configured byusing bipolar transistors in the present invention.

While the present invention has been described with reference toexemplary embodiments, it is to be understood that the invention is notlimited to the disclosed exemplary embodiments. The scope of thefollowing claims is to be accorded the broadest interpretation so as toencompass all such modifications and equivalent structures andfunctions.

This application claims the benefit of Japanese Patent Application No.2007-021439, filed Jan. 31, 2007, which is hereby incorporated byreference herein in its entirety.

1. A differential signal comparator for converting difference voltagebetween complementary input signals into a voltage of CMOS level,wherein the complementary input signals are input into first and seconddifferential amplifier circuits complementary to each other, the firstdifferential amplifier circuit outputs first and second currents, thesecond differential amplifier circuit outputs third and fourth currents,the first and second currents are output into first and second currentamplification circuits, the third and fourth currents are output intothird and fourth current amplification circuits, outputs from the firstto fourth current amplification circuits are input into a currentarithmetic operation circuit, the current arithmetic operation circuitoutputs complementary current based on the complementary input signals,the complementary current output is current-voltage converted, and theconverted signal is input into a differential comparator of CMOS levelinput, and further converted into a single end CMOS level output.
 2. Thedifferential signal comparator according to claim 1, further comprising:a first current mirror circuit for outputting two series of currentsbeing k times as large as the first current based on the first current,a second current mirror circuit for outputting two series of currentsbeing k times as large as the second current based on the secondcurrent, a third current mirror circuit for outputting a current being mtimes as large as the third current based on the third current, a fourthcurrent mirror circuit for outputting a current being m times as largeas the fourth current based on the fourth current, a fifth currentmirror circuit for outputting two series of currents being n times aslarge as an output current from the third current mirror circuit basedon the output current from the third current mirror circuit, a sixthcurrent mirror circuit for outputting two series of currents being ntimes as large as an output current from the fourth current mirrorcircuit based on the output current from the fourth current mirrorcircuit, a seventh current mirror circuit for inputting output currentsfrom the first and fifth current mirror circuits and for outputting acurrent based on the output currents from the first and fifth currentmirror circuits, and an eighth current mirror circuit for inputtingoutput currents from the second and sixth current mirror circuits andfor outputting a current based on the output currents from the secondand sixth current mirror circuits, wherein a first differential currentis produced by combining the output currents from the first, fifth andseventh current mirror circuits, a second differential currentcomplementary to the first differential current is produced by combiningthe output currents from the second, sixth and eighth current mirrorcircuits, and the differential comparator inputs the first and seconddifferential currents and convert them into the single end CMOS leveloutput.
 3. The differential signal comparator according to claim 2,wherein k, m and n meet relation: k=m×n.
 4. The differential signalcomparator according to claim 1, wherein the first differentialamplifier circuit has first and second PMOS transistors, and a firstconstant current source connected to a node to which sources of thefirst and second PMOS transistors are connected commonly, the seconddifferential amplifier circuit has first and second NMOS transistors,and a second constant current source connected to a node to whichsources of the first and second NMOS transistors are connected commonly,a drain of the first PMOS transistor is connected to an input of thefirst current mirror circuit, a drain of the second PMOS transistor isconnected to an input of the second current mirror circuit, a drain ofthe first NMOS transistor is connected to an input of the third currentmirror circuit, a drain of the second NMOS transistor is connected to aninput of the fourth current mirror circuit, gates of the first PMOStransistor and the first NMOS transistor are commonly connected, andconnected to one of the input terminals, and gates of the first NMOStransistor and the second NMOS transistor are commonly connected, andconnected to the other of the input terminals.